Raytheon Technologies Manager III Electrical Engineering - ASIC Design in El Segundo, California
Raytheon Intelligence and Space Systems is seeking a Digital ASIC Section Manager to lead a new section passionate on Digital ASIC design in support of future sensor systems, communication systems and other emerging business areas for our nation’s next generation security and defense platforms.
Providing oversight to a team of skilled Digital ASIC designers, growing and mentoring the team, matching resources to program/project needs and providing oversight of work products.
Three quarters of the Section Manager's time will be committed to guide work on programs. Roles would include Principal Investigator/lead Digital ASIC Engineer, Integrated Product Team Lead (IPTL), individual contributor, and/or technical reviewer.
The Section Manager will interact frequently with team leads and Chief Engineers to ensure that the section is meeting the needs of its internal and external customers and the Electronics Center.
The Section Manager will need to be an effective communicator, leader, and decision maker as well as an excellent advocate for process improvement, diversity in team shaping, and have high professional standards.
The Section Manager role shall demonstrate that the section effectively uses Robust Design, Agile Design principles and the expertise of Product Owners in delivery of work to Integrated Product Team Leads.
The Section Manager will work closely with the Microelectronics Department Manager in support of Department, Engineering and Raytheon goals/objectives
Minimum 10 years of Digital ASIC design and verification experience.
Expertise in custom digital integrated circuit design from architecture refinement, RTL coding, verification in a UVM environment, thru synthesis and generation of timing constraints.
Deep understanding of the ASIC design process, and fully understanding of the implication of design choices thru the entire design process.
Knowledge of the latest technology trends in the area of high speed FinFet CMOS circuit design resources and methodologies including high level synthesis instruments and the latest verification methodologies.
Working knowledge of low power design methodologies, digital physical design, floor-planning, place and route, DFM, DFT, timing closure and release to manufacturing.
Synthesis using Cadence Genus or equivalent resource, and familiar with physical aware synthesis and low power tools and techniques.
Excellent communication (oral and written) skills
Ability to present to and interface with customers (internal and external).
Ability to handle an adaptable environment and to coordinate team actions
Bachelor’s Degree in Electrical Engineering or closely related discipline is required.
BS and 10 years of experience, MS and 8 years of experience, PhD and 6 years of experience.
Masters’ Degree in Electrical Engineering or closely related discipline is preferred
U.S. Citizenship status is required as this position will need a U.S. Security Clearance within 1 year of start date.
This position requires either a U.S. Person or a Non-U.S. Person who is eligible to obtain any required Export Authorization.
Raytheon is an Equal Opportunity/Affirmative Action employer. All qualified applicants will receive consideration for employment without regard to race, age, color, religion, creed, sex, sexual orientation, gender identity, national origin, disability, or protected Veteran status.